An optimization technique for dual-output domino logic

Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. One well-known dynamic logic family is the domino CMOS family, which, however, suffers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is the dual-output domino logic family. The authors discuss an optimization technique for this logic family.