A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS

Author

Scheir, K. ; Bronckers, S. ; Borremans, J. ; Wambacq, P. ; Rolain, Y.

Author_Institution

IMEC, Leuven

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

184

Lastpage

605

Abstract

In this paper, a CMOS implementation of phased-array receiver front-end, based on a widely tunable QVCO is presented. Each path achieves 30dB of gain and a minimum NF of 7.1dB, yielding a system NF of 4.1dB. The overall current draw is 54mA from a 1.2V supply. Additionally, a calibration procedure to mitigate the analog impairments imposed by the proposed implementation is demonstrated.

Keywords

CMOS integrated circuits; antenna phased arrays; calibration; millimetre wave antenna arrays; millimetre wave integrated circuits; millimetre wave receivers; voltage-controlled oscillators; analog impairments mitigation; calibration procedure; current 54 mA; digital CMOS; frequency 52 GHz; gain 30 dB; noise figure 4.1 dB; noise figure 7.1 dB; phased-array receiver front-end; size 90 nm; voltage 1.2 V; widely tunable QVCO; Array signal processing; Digital control; Energy consumption; Frequency conversion; Frequency measurement; Gain measurement; Noise measurement; Phased arrays; Radio frequency; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523118

Filename

4523118