Title :
VHDL synthesis of a 0.7 μ CMOS ASIC for block segmentation of digital images
Author :
Huylebroeck, J. ; Martiny, D. ; Boekaerts, P. ; Cornelis, Jens
Author_Institution :
Dept. of Electron., Vrije Univ., Brussels, Belgium
Abstract :
Commercially available VHDL synthesis tools can handle the functional complexity of block segmentation. The resulting ASIC´s, implemented in 0.7 μ CMOS technology, may easily be integrated in a test processing card that speeds up the block segmentation of grey value images with a factor 100 compared to the performance of a PC DX2
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; hardware description languages; image segmentation; integrated circuit design; 0.7 micron; CMOS ASIC; VHDL synthesis; block segmentation; digital image; Algorithm design and analysis; Application specific integrated circuits; Convergence; Digital images; Functional programming; Image segmentation; Labeling; Logic; Pixel; Testing;
Conference_Titel :
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location :
Rodos
Print_ISBN :
0-7803-3650-X
DOI :
10.1109/ICECS.1996.584541
