Design of a 3rd order micro power switched current ΣΔ-modulator

This paper reports the design of a 3rd order switched current-ΣΔ-modulator. The modulator is design to have a SNR of 80 dB with a signal bandwidth of f_b=6 kHz. The oversampling ratio is R=90 and the sampling frequency f_s=1.08 MHz. Multiple input signals are used to reduce the internal signal swings, which results in reduced power consumption. The noise from the 2nd and 3rd integrator is shaped. This is used to allow the noise power from these integrators to be increased and hence saving power. The power consumption of the first integrator is 254 μW and the total power consumption is 600 μW. The supply voltage is V_DD=2.7 V. A new methology is presented that allows for optimization of SI circuits for minimum power consumption with respect to process tolerances