• DocumentCode
    3463562
  • Title

    A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

  • Author

    Chang, Hsiang-Hui ; Wang, Ping-Ying ; Zhan, Jing-Hong Conan ; Hsieh, Bing-Yu

  • Author_Institution
    MediaTek, Hsinchu
  • fYear
    2008
  • fDate
    3-7 Feb. 2008
  • Firstpage
    200
  • Lastpage
    606
  • Abstract
    This paper presents a 3.2-to-4GHz fractional spur-free ADPLL. The ADPLL is fabricated in a 0.13 mum CMOS process and packaged in QFN76. Fractional spurs are filtered by accurate digital loop-gain calibration and digital phase-noise cancellation. The ADPLL is designed to minimize the switching noise while taking advantage of digital scaling.
  • Keywords
    3G mobile communication; CMOS digital integrated circuits; cellular radio; digital phase locked loops; integrated circuit packaging; packet radio networks; phase noise; telecommunication standards; CMOS process; EDGE; GPRS; GSM; QFN76; all digital phase-locked loop; digital scaling; fractional spur-free ADPLL; frequency 3.2 GHz to 4 GHz; loop-gain calibration; phase-noise cancellation; size 0.13 mum; switching noise; 1f noise; Calibration; Capacitors; Digital control; Digital filters; Feedforward systems; Frequency; GSM; Ground penetrating radar; Noise cancellation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-2010-0
  • Electronic_ISBN
    978-1-4244-2011-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2008.4523126
  • Filename
    4523126
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3463562