• DocumentCode
    3463588
  • Title

    Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function

  • Author

    Malamas, E.N. ; Paliouras, V. ; Stouraitis, T.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Patras Univ., Greece
  • Volume
    2
  • fYear
    1996
  • fDate
    13-16 Oct 1996
  • Firstpage
    964
  • Abstract
    In this paper, algorithms and architectures for the evaluation of trigonometric functions in the Logarithmic Number System (LNS) are described. A novel algorithm for the computation of the LNS cosine, based on the subtraction function, is presented and extended to compute all trigonometric functions. The proposed algorithms show a major advantage over other methods in terms of memory requirements (up to 94% improvement as opposed to direct polynomial approximation) and computational speed. A hardware implementation of an elementary LNS trigonometric processor with 12-bit accuracy is also presented, to illustrate the feasibility of extending the LNS processors to include trigonometric functions
  • Keywords
    VLSI; arithmetic; functions; LNS processor; VLSI architecture; algorithm; cosine; logarithmic number system; subtraction function; trigonometric function; Algorithm design and analysis; Arithmetic; Computer architecture; Digital signal processing; Hardware; Laboratories; Partitioning algorithms; Polynomials; Shape; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
  • Conference_Location
    Rodos
  • Print_ISBN
    0-7803-3650-X
  • Type

    conf

  • DOI
    10.1109/ICECS.1996.584546
  • Filename
    584546