A thermally activated gate current in off-state PMOSFETs

Using buried-channel PFET devices with lightly doped drains (LDDs), the authors study the gate current and the threshold-voltage instability at intermediate electric fields and as a function of temperature. Although the same effects occur on surface-channel devices, larger potential differences were required because the built-in potential difference between N+ and P+ diffusions increases gate-induced diffusion leakage (GIDL) in buried-channel devices. Gate current was measured over a wide range of voltage and temperature on large gate perimeter PMOSFET devices. The measurements revealed a gate current with a voltage and temperature dependence proportional to the GIDL current. Hot electron stressing suggests the trapped charge is located near the gate-drain overlap region for short channel devices and near the intersection of the gate-drain overlap and the trench convex corner for narrow trench isolated devices.<>