Author :
Staszewski, R.B. ; Leipold, D. ; Eliezer, O. ; Entezari, M. ; Muhammad, K. ; Bashir, I. ; Hung, C.-M. ; Wallberg, J. ; Staszewski, R. ; Cruise, P. ; Rezeq, S. ; Vemulapalli, S. ; Waheed, K. ; Barton, N. ; Lee, M.-C. ; Fernando, C. ; Maggio, K. ; Jung, T.
Abstract :
The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.
Keywords :
CMOS digital integrated circuits; cellular radio; crystal oscillators; digital signal processing chips; discrete time systems; transceivers; ADPLL; DSP technique; RF transceiver; digital CMOS; digital RF processor technology; digital controlled crystal oscillator; discrete-time architecture; frequency 26 MHz; quadband single-chip GSM radio; transmitter calibration; Calibration; GSM; Ground penetrating radar; Phase noise; Power generation; Predistortion; Radio frequency; Timing jitter; Transceivers; Voltage;
