A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells

PON is one of the promising solutions for the last-mile communication systems. In PONs, the fast-locked CDR circuit must lock within tens of bit times once the data packets arrive. The so-called burst-mode CDR (BMCDR) circuits with gated VCOs (GVCOs) have been presented. To meet the requirements of different PON standards, a multi-band BMCDR circuit is very desirable. The conventional multi-band technique is realized by a GVCO with dividers. Since the GVCO has to operate at the highest speed, it dissipates a fixed power, even though only a low data rate is required. Furthermore, the dividers introduce extra time delays to reduce the sampling margin that may become an issue for high data rates. In this work, a 20/10/5/2.5Gb/s power-scaling BMCDR circuit is implemented in 90nm CMOS technology. It is aimed to scale the power of a BMCDR circuit for different data rates. To realize a power-scaling multi-band BMCDR circuit, a tri-mode cell can be configured as a GVCO, a divide-by-2 divider, or 2 DFFs. Moreover, improvements are made to address the problem associated with the extra time delays that reduce the sampling margin.