Implementation of a low power decimation filter using 1/3-band IIR filter

This paper presents a unique design and implementation of a low power decimation filter. The designed decimation filter architecture shows how the 1/3-band IIR filter and a poly-phase half-band FIR filter are used multirate multistage signal processing. The 1/3-band IIR filter is realized using six first order all-pass filters. Each filter stage is simulated using Matlab and, the complete architecture of the decimation filter is captured using Simulink and a DSP blockset. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The designed decimation filter reduces the hardware by 59% and the power dissipation by 34% compared to conventional decimation filters.