Title :
New three-dimensional integration technology to achieve a super chip
Author :
Koyanagi, Mitsumasa ; Fukushima, Takafumi ; Tanaka, Tetsu
Author_Institution :
Dept. of Bioeng. & Robotics, Tohoku Univ., Sendai
Abstract :
We have proposed a new three-dimensional (3D) integration technology based on a chip-to-wafer bonding method which is called a super chip integration technology. Various kinds of chips such as processor chip, memory chips, analog IC chip and sensor chips which are fabricated by different technologies can be vertically stacked into a 3D LSI chip by using a super chip integration technology. Such 3D LSI chip is called a super chip. Various kinds of chips with different chip size, chip thickness and material can be vertically stacked in the super chip integration technology. To establish the super chip integration technology, several key technologies of vertical interconnection formation, chip alignment and bonding, adhesive injection, and chip thinning and planarization were developed. By using the super chip integration technology, three-layer stacked LSI chips with vertical interconnections were successfully fabricated
Keywords :
adhesive bonding; integrated circuit interconnections; large scale integration; microprocessor chips; system-on-chip; 3D LSI chip; 3D integration technology; adhesive injection; analog IC chip; chip alignment; chip size; chip thickness; chip thinning; chip-to-wafer bonding; memory chips; planarization; processor chip; sensor chip; super chip integration; vertical interconnection formation; Analog integrated circuits; Conducting materials; Etching; Fabrication; Gold; Large scale integration; Planarization; Plasma applications; Resists; Wafer bonding;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306217
