Title :
Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS
Author :
Ginsburg, Brian P. ; Chandrakasan, Anantha P.
Author_Institution :
Texas Instrum., Dallas, TX
Abstract :
The 250 MS/S ADC has 36 time-interleaved 5b SAR ADC channels operating at 800 mV. Parallelism is used specifically to improve energy efficiency, and architectural solutions address the limitations of interleaving. Redundancy is used as an efficient technique to counteract the yield loss from local variation. A hierarchical top- plate sampling network reduces timing skew with extended sampling times and permits a partitioned clock network for minimum distribution requirements.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS process; hierarchical top- plate sampling network; highly interleaved ADC; partitioned clock network; redundant channels; size 65 nm; successive approximation ADC channels; voltage 800 mV; Capacitors; Clocks; Crosstalk; Parasitic capacitance; Performance evaluation; Sampling methods; Solid state circuits; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523146
