Title :
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC
Author :
Van der Plas, Geert ; Verbruggen, Bob
Author_Institution :
lMEC, Leuven
Abstract :
In this paper, a 2-step 7b ADC consists of a TVH, followed by a 1b comparison and D/A conversion, and a 6b comparator-based asynchronous binary-search (CABS) conversion. The 7b ADC operates as follows: the passive T/H samples the input signal on a capacitance, the 1b comparator determines the sign of the input and steers a capacitive DAC. The DAC subtracts 1/4 of the full-scale range in charge from one of the input nodes, changing simultaneously differential signal and common-mode level to be in range of the 6b CABS converter. The clock buffer generates the 1b coarse A/D clock signal and starts the 6b fine conversion after the 1b D/A conversion has finished.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); A/D clock signal; ADC; CABS; analog-digital conversion; clock buffer; comparator-based asynchronous binary-search conversion; digital CMOS process; passive T/H samples; power 133 muW; size 90 nm; Calibration; Clocks; Frequency; Parasitic capacitance; Programmable logic arrays; Quantization; Routing; Sampling methods; Solid state circuits; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523147
