Title :
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic
Author :
Cheng, Kuo-Hsing ; Yee, Liow Yu
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Abstract :
This work describes a CMOS 8*8-bit parallel multiplier for 1.2 V supply voltage. The low-power current-sensing complementary pass-transistor logic (LCSCPTL) is applied to the design of the parallel multiplier. The LCSCPTL have certain advantages in both speed and power dissipation over the CPL circuit. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V low-voltage 8*8-bit parallel multiplier can be designed and fabricated without changing the conventional 5 V 0.8 m CMOS process. Based upon the HSPICE simulation results, the operation speed of the parallel multiplier is 54 ns for 1.2 V supply voltage
Keywords :
CMOS logic circuits; multiplying circuits; 0.8 micron; 1.2 V; 4-2 compressor; 54 ns; 8 bit; CMOS parallel multiplier; HSPICE simulation; LCSCPTL; conditional carry selection; low-power current-sensing complementary pass-transistor logic; operation speed; power dissipation; CMOS logic circuits; CMOS process; Digital circuits; Logic circuits; Logic design; MOS devices; MOSFETs; Power dissipation; Power supplies; Voltage;
Conference_Titel :
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location :
Rodos
Print_ISBN :
0-7803-3650-X
DOI :
10.1109/ICECS.1996.584564
