Title :
A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
Author :
Agnes, Andrea ; Bonizzoni, Edoardo ; Malcovati, Piero ; Maloberti, Franco
Author_Institution :
Univ. of Pavia, Pavia
Abstract :
The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); CMOS process; SAR ADC; conversion-step FOM; figure-of-merit; power 3.8 muW; size 0.18 mum; successive approximation ADC; time-domain comparator; voltage 1 V; Capacitance; Capacitors; Circuits; Clocks; Energy consumption; Frequency; Logic arrays; Switches; Time domain analysis; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523149
