A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Author

Yun, Won-Joo ; Lee, Hyun Woo ; Shin, Dongsuk ; Kang, Shin Deok ; Yang, Ji Yeon ; Lee, Hyeng Ouk ; Lee, Dong Uk ; Sim, Sujeong ; Kim, Young Ju ; Choi, Won Jun ; Song, Keun Soo ; Shin, Sang Hoon ; Choi, Hyang Hwa ; Moon, Hyung Wook ; Kwack, Seung Wook ; Lee

Author_Institution

Hynix Semicond., Icheon

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

282

Lastpage

613

Abstract

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.

Keywords

CMOS integrated circuits; DRAM chips; clocks; delay lock loops; CMOS technology; DRAM chips; all-digital DLL; clock receiver; digital controlled duty-cycle-error detector; duty-cycle correction circuit; frequency 0.1 GHz to 1.5 GHz; power 4.2 mW; size 66 nm; update gear circuit; CMOS technology; Circuits; Clocks; Detectors; Energy consumption; Gears; Random access memory; Space vector pulse width modulation; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523167

Filename

4523167