Run-time scheduler synthesis for hardware-software systems and application to robot control design

We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level specification in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in software, thus supporting features typical of software schedulers. We describe the tool flow and target architecture, synthesis of the control portion of the run-time scheduler in hardware, and control of the software using interrupts. Finally, we conclude with a sample application of the tool to a robot design example