A new punch through IGBT having a new N-buffer layer

Author

Iwamoto, Hideo ; Haruguchi, Hideki ; Tomomatsu, Yoshifumi ; Donlon, John F. ; Motto, Eric R.

Author_Institution

Mitsubishi Electr. Corp., Fukuoka, Japan

Volume

1

fYear

1999

fDate

1999

Firstpage

692

Abstract

IGBTs based on the NPT (nonpunch through) design approach exhibit excellent safe operating area and short circuit endurance, a positive temperature coefficient of on-state voltage over the operating current range, and low silicon cost. These merits have supported the development and commercialization of NPT IGBTs above the 1200 Volt class. However, the need for quite thin silicon to obtain competitive on-state losses at 1200 volt and below classes has hindered the use of the NPT approach in this area. A new punch through (PT) IGBT has been developed which exhibits the merits of the NPT approach, rugged SOA and short circuit endurance, while also having a better trade-off relation between on-state voltage and turn-off loss than either existing NPT or third generation PT IGBT

Keywords

insulated gate bipolar transistors; losses; short-circuit currents; N-buffer layer; low silicon cost; on-state losses; on-state voltage; operating current range; positive temperature coefficient; punch through IGBT; safe operating area; short circuit endurance; turn-off loss; Breakdown voltage; Circuits; Costs; Design engineering; Insulated gate bipolar transistors; Leakage current; Power engineering and energy; Semiconductor optical amplifiers; Silicon; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Industry Applications Conference, 1999. Thirty-Fourth IAS Annual Meeting. Conference Record of the 1999 IEEE

Conference_Location

Phoenix, AZ

ISSN

0197-2618

Print_ISBN

0-7803-5589-X

Type

conf

DOI

10.1109/IAS.1999.800025

Filename

800025