Title :
Laser annealing technology and device integration challenges
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo
Abstract :
We investigated impacts of halo and deep source/drain junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. We have also developed a novel laser thermal processing (LTP) that dramatically enhances laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit
Keywords :
laser beam annealing; semiconductor devices; semiconductor junctions; device integration challenges; halo optimization; hot carrier degradation; laser annealing technology; laser exposure window; laser thermal processing; nonmelt laser spike annealing; CMOS process; Epitaxial growth; Heating; Interference; Laboratories; Lamps; Laser theory; Rapid thermal annealing; Rapid thermal processing; Solids;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306299