A turbo/MAP decoder for use in satellite circuits

Author

Pietrobon, Steven S.

Author_Institution

Small World Commun., Payneham South, SA, Australia

Volume

1

fYear

1997

fDate

9-12 Sep 1997

Firstpage

427

Abstract

The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E_b/N₀ of 0.32 and -0.30 dB, respectively for a BER of 10^-5. BERs down to 10^-7 were also achieved for a small increase in E_b/N₀

Keywords

codecs; concatenated codes; convolutional codes; decoding; error correction codes; satellite communication; 356 kbit/s; 65536 bit; BER; EPROM; MAP decoder; bit error rate; codec; decoding stages; interleaver block sizes; logarithm domain; programmable gate arrays; satellite circuits; state codes; turbo decoder; Australia; Bit error rate; Circuits; Codecs; Error correction; Interference; Iterative algorithms; Iterative decoding; Satellites; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Information, Communications and Signal Processing, 1997. ICICS., Proceedings of 1997 International Conference on

Print_ISBN

0-7803-3676-3

Type

conf

DOI

10.1109/ICICS.1997.647132

Filename

647132