Title :
A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection
Author :
Ru, Z. ; Klumperink, E.A.M. ; Nauta, B.
Author_Institution :
Enschede, Univ. of Twente, Enschede
Abstract :
The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3rd and 5th harmonic mixing. An inverter-based RF-amplifier (RFA) drives a passive switched-capacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, second stage consists of I/Q DT mixers for downconversion and the third stage is a low-pass IIR filter. The chip fabricated in a 65nm CMOS process occupies an active area of 0.36mm2. The noise and linearity performances are competitive with those of continuous-time mixers at reasonable power consumption, which shows the feasibility of the proposed architecture for a practical receiver front-end.
Keywords :
CMOS integrated circuits; IIR filters; broadband networks; cognitive radio; digital video broadcasting; harmonics suppression; mixers (circuits); radio receivers; radiofrequency amplifiers; switched capacitor networks; television standards; CMOS process; DVB-H standard; I-Q DT mixers; SDR downconverter; chip fabrication; cognitive radio applications; discrete-time mixing receiver architecture; frequency 200 MHz to 900 MHz; harmonic mixing; inverter-based RF-amplifier; low-pass IIR filter; oversampler; passive switched-capacitor; receiver front-end; size 65 nm; wideband harmonic rejection; CMOS process; Capacitors; Clocks; Finite impulse response filter; Power harmonic filters; Radio frequency; Receivers; Semiconductor device measurement; Signal sampling; Wideband;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523187
