DocumentCode
3464825
Title
Low-power digital PLL with one cycle frequency lock-in time and large frequency-multiplication factor for advanced power management
Author
Fried, Rafael ; Azmanov, Ziv
Author_Institution
Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Lausanne, Switzerland
Volume
2
fYear
1996
fDate
13-16 Oct 1996
Firstpage
1166
Abstract
A low-power Digital PLL (DPLL) with +/-100 ps jitter and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a 32,768 Hz reference clock. The DPLL is especially designed for advanced power management and performance enhancement, both at a chip level and system level
Keywords
CMOS digital integrated circuits; digital phase locked loops; jitter; timing circuits; 100 MHz; 32768 Hz; clock frequency generation; frequency-multiplication factor; jitter; low-power digital PLL; one cycle frequency lock-in time; power management; Batteries; Clocks; Control systems; Costs; Energy management; Frequency conversion; Personal communication networks; Phase locked loops; Power system management; Thermal management;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location
Rodos
Print_ISBN
0-7803-3650-X
Type
conf
DOI
10.1109/ICECS.1996.584629
Filename
584629
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