A low-voltage reduced-power constant-gm rail-to-rail fully differential CMOS op-amp

A new low-voltage low-power fully differential operational amplifier in 0.7 μm standard CMOS (threshold voltages of about 0.75 V) with constant-g_m and rail-to-rail input and output stages is presented. It is a varied version of a fully differential integrated circuit, where the power consumption has been decreased by an internal circuitry working only in the case of a differential input voltage. Performance comparable to that of the “normal” fully differential structure can be obtained but with a power reduction of about 30% when only common mode signals are applied. It is possible to reduce further the power consumption until to about 50%, using the same topology and acting on transistor sizes, but with a small degradation of the op-amp performance. The minimum supply voltage is 1.2 V. The unity gain frequency is about 1.12 MHz (with a Miller capacitance of 10 pF) and the DC voltage gain of the differential op-amp is about 60 dB, with a total power dissipation of about 0.52 mW. In the case of minimized power (360 μW) design, the gain bandwidth becomes 350 KHz and the voltage gain is 54 dB