A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities

Author

Maxim, A. ; Poorfard, R. ; Reid, M. ; Kao, J. ; Thompson, C. ; Johnson, R.

Author_Institution

Silicon Labs., Austin, TX

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

372

Lastpage

621

Abstract

The proposed DDFS-driven mixing-DAC consists of several parallel-connected Gilbert cells driven directly by the binary and thermometer DDFS data compromise between power-dissipation and harmonic-rejection performance is achieved with 5b binary LSBs and 5b thermometer MSBs segmented mixing-DAC. The 2.8-to-3.2 GHz DDFS sampling frequency is selected such that it provides in excess of two samples per cycle up to 1 GHz, while the LO sampling spurs (fsplusmnfL0) are always outside the receiver desired frequency band. It is dynamically adjusted for each received channel to minimize in-band DDFS induced spurs.

Keywords

UHF integrated circuits; UHF mixers; digital-analogue conversion; direct digital synthesis; thermometers; 5b binary LSB; 5b thermometer MSB; DDFS driven mixing-DAC; DDFS sampling frequency; digital-frequency-synthesizers; frequency 2.8 MHz to 3.2 MHz; harmonic rejection performance; parallel-connected Gilbert cells; power-dissipation; thermometer DDFS data; Clocks; Delay; Linearity; Parasitic capacitance; Phase locked loops; Power harmonic filters; Radio frequency; Resistors; Tuners; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523212

Filename

4523212