Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter

Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90 nm technology using a static CMOS implementation. In this work, we present an unrolled ΣΔ architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.