Title :
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management
Author :
Pilo, Harold ; Ramadurai, Vinod ; Braceras, Geordie ; Gabric, John ; Lamphier, Steve ; Tan, Yue
Author_Institution :
IBM, Essex Junction, VT
Abstract :
A 450 ps access-time 512 Kb SRAM macro is fabricated in a 45 nm SOI technology. The macro is adapted for use as the principal growable embedded-SRAM block in a 45 nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements.
Keywords :
SRAM chips; application specific integrated circuits; integrated circuit design; low-power electronics; silicon-on-insulator; ASIC; SOI technology; SRAM macro; Si-SiO2; dynamic power management; leakage power consumption; single-device dynamic-leakage-suppression scheme; size 45 nm; time 450 ps; two-stage body-contacted sensing scheme; two-stage sensing-scheme; CMOS technology; Capacitance; Decoding; Delay; Energy consumption; Energy management; Logic devices; Power supplies; Random access memory; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523215
