Very high precision Vernier delay line based CMOS pulse generator

This paper describes a wide range, area efficient, high precision pulse generator, which has applications in ultrawideband communications and VLSI testing. The proposed architecture exploits Vernier delay line method, which is a popular technique used for very fine time digitization. In the proposed method, width of the generated pulse is programmable to the nearest multiple of a constant buffer delay and finer incremental pulse width, less than one buffer delay is generated using Vernier delay line. The pulse generator architecture was designed, simulated and validated using SPICE in 0.18 μm CMOS technology and achieves a resolution less than 10 ps. The pulse generator can be programmed to generate pulses with a minimum pulse width of 160 ps and an incremental pulse width of 10 ps in CMOS 0.18 μm technology.