Yield aware design methodology for sub-100-nanometer digital SOC designs

Designing multi-GHz high-speed digital design blocks, using corner based digital design methodology pushes the performance limits to the extreme and provides the designers with very limited insight on the yield issues, with respect to process variation vulnerabilities. In this paper, we propose a statistically aware methodology, for designing high speed digital design blocks, which not only takes into account the process variability but also ensures a yield of -99.5% . We have tested the distribution based methodology on simple digital blocks and compared the results to the existing corner based approach. We also performed these runs on a timing-critical design of a time-to-digital converter (TDC) block and representative paths from a high-speed control unit block of a SoC wireless design and verified that these designs met the performance metrics at the sigma points with -99.5% yield.