The Alpha 21164PC microprocessor

Author

Bannon, P. ; Saito, Y.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1997

fDate

23-26 Feb. 1997

Firstpage

20

Lastpage

27

Abstract

The internal architecture of a 2000 MIPS/1000 MFLOPS (peak) high performance low cost CMOS Alpha microprocessor chip is described. This implementation is derived from the Alpha 21164 microprocessor to reduce cost while maintaining high performance. It contains a quad issue superscalar instruction unit, two 64 bit integer execution pipelines, and two 64 bit floating point execution pipelines. The memory unit and bus interface unit have been redesigned to provide a high performance memory system using industry standard PC SRAM and DRAM components.

Keywords

CMOS integrated circuits; instruction sets; integrated memory circuits; microprocessor chips; pipeline processing; 1000 MFLOPS; 2000 MIPS; 64 bit; Alpha 21164PC microprocessor; DRAM components; bus interface unit; floating point execution pipelines; high performance low cost CMOS Alpha microprocessor chip; high performance memory system; industry standard PC SRAM; integer execution pipelines; internal architecture; memory unit; quad issue superscalar instruction unit; CMOS process; Ceramics; Costs; Logic; Microprocessors; Packaging; Pins; Pipelines; Random access memory; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon '97. Proceedings, IEEE

Conference_Location

San Jose, CA, USA

ISSN

1063-6390

Print_ISBN

0-8186-7804-6

Type

conf

DOI

10.1109/CMPCON.1997.584665

Filename

584665