A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm

Author

Cernea, Raul ; Pham, Long ; Moogat, Farookh ; Chan, Siu ; Le, Binh ; Li, Yan ; Tsao, Shouchang ; Tseng, Tai-Yuan ; Nguyen, Khanh ; Li, Jason ; Hu, Jayson ; Park, Jong ; Hsu, Cynthia ; Zhang, Fanglin ; Kamei, Teruhiko ; Nasu, Hiroaki ; Kliza, Phil ; Htoo,

Author_Institution

SanDisk Corp., Milpitas, CA

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

420

Lastpage

624

Abstract

In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for actual operations, every other cell along a selected word line (WL) (Takeuchi, 2006), this design simultaneously exercises them all. A performance improvement of at least 100% is derived from this all-bitline (ABL) architecture relative to conventional chips. Additional techniques push performance to even higher levels.

Keywords

NAND circuits; flash memories; memory architecture; ABL architecture; MLC NAND; NAND flash; all-bitline architecture; bit rate 34 Mbit/s; size 56 nm; word line; Circuits; Decoding; Diodes; Latches; Logic; MOS devices; MOSFETs; Nonvolatile memory; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523236

Filename

4523236