Title :
A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface
Author :
Nobunaga, Dean ; Abedifard, Ebrahim ; Roohparvar, Frankie ; Lee, June ; Yu, Erwin ; Vahidimowlavi, Allahyar ; Abraham, Michael ; Talreja, Sanjay ; Sundaram, Rajesh ; Rozman, Rod ; Vu, Luyen ; Chen, Chih Liang ; Chandrasekhar, Uday ; Bains, Rupinder ; Viaj
Author_Institution :
Micron, San Jose, CA
Abstract :
A 3.3V 8Gb NAND flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of the markets. This paper achieves a NAND flash program throughput of 100 MB/s with quad-plane operation, which is 5x previously reported. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface and data path. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND flash interface.
Keywords :
NAND circuits; flash memories; I/O read/write throughput; NAND flash memory; double-data-rate interface; program throughput; quad-plane operation; size 50 nm; synchronous DDR interface; voltage 3.3 V; CMOS memory circuits; CMOS technology; Clocks; Interleaved codes; Prefetching; Registers; Solid state circuits; Synchronization; Throughput; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523239
