DocumentCode
3465818
Title
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator
Author
Kim, Kyu-hyoun ; Coteus, Paul W. ; Dreps, Daniel ; Kim, Seongwon ; Rylov, Sergey V. ; Friedman, Daniel J.
Author_Institution
IBM T.J. Watson, Yorktown Heights, NY
fYear
2008
fDate
3-7 Feb. 2008
Firstpage
458
Lastpage
627
Abstract
In this paper, a wide frequency open-loop quadrature generator is sufficiently compact to allow many stages to be cascaded affordably. The generator is built from cascaded quad corrector stages, each of which in turn, can be understood as a modification of a common interpolating 4-stage ring oscillator. In the circuit, the delay of each stage is a linear superposition of the delays Phi of the associated inner and outer loop elements. If the outer loop element inputs are made independent, the driven oscillator is resulted. Provided the input drive is sufficient, the frequency of the driven oscillator is that of the driving input, and the phase of each internal node is an interpolation of the phase of its input drive and the phase of the preceding stage. This interpolation acts to average offsets from quadrature in the incoming phases. If the input drive is insufficient, the oscillator will run near its natural or unloaded frequency, omega0=2pifo.
Keywords
clocks; interpolation; oscillators; 4-stage ring oscillator; cascaded quad corrector stages; linear superposition; open-loop quadrature clock generator; outer loop element inputs; Circuit simulation; Clocks; Cutoff frequency; Delay; Design optimization; Inverters; Power harmonic filters; Predictive models; Ring oscillators; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-2010-0
Electronic_ISBN
978-1-4244-2011-7
Type
conf
DOI
10.1109/ISSCC.2008.4523255
Filename
4523255
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