A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS

As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels. This has also served as a standard benchmark vehicle that reveals high-speed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled, and they are comparable to dividers in other technologies. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the f_{div , max}, the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the f_{div , max}, since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.