An 8Ã\x973.2Gb/s Parallel Receiver with Collaborative Timing Recovery

This paper explores the architecture and design of an 8x3.2 Gb/s parallel receiver that relies on collaborative timing recovery. Given synchrony between parallel data channels, per-channel clock recovery can be replaced by a single global timing-recovery (TR) block to save power. Moreover, collecting timing-error information across all of the data channels greatly enhances effective edge transition density, which decreases dithering jitter on the recovered clock.