DocumentCode
3466075
Title
Future trends in charge trapping memories
Author
Kuesters, K.-H. ; Ludwig, C. ; Mikolajick, T. ; Nagel, N. ; Specht, M. ; Pissors, V. ; Schulze, N. ; Stein, E. ; Willer, J.
Author_Institution
Qimonda Dresden GmbH & Co. OHG
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
740
Lastpage
743
Abstract
Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques
Keywords
flash memories; read-only storage; 50 nm; NROM memories; SONOS memories; charge trapping memories; data flash memories; floating gate technique; Costs; Dielectric materials; Electron traps; Flash memory; High K dielectric materials; High-K gate dielectrics; Nonvolatile memory; Production; SONOS devices; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306473
Filename
4098221
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