A fast bitline capacitance evaluation method for designing ferroelectric random access memory

One major issue of designing ferroelectric random access memory is to ascertain the proper ferroelectric capacitor scales for predefined capacity and architecture. Prior to that, bitline capacitor should be calculated accurately. In this paper, the topology of parasite capacitance in a typical 2T2C reading operation is analyzed, and an applicable bitline capacitance evaluation method is proposed. Applying this method on the test chip with 2T2C configuration, optimized ferroelectric capacitance could be acquired