Performance improvement of MS synchronization network with an average number increased along hierarchy

Proposes a hierarchical MS (master-slave) synchronization network in which the average number of phase errors of the slaves increases along the hierarchy, in order to improve both jitter suppression and phase tracking of the overall network. The network is compared with the conventional network, which uses the same average number of phase errors for all hierarchical slaves. The results show that with the same tracking property, the jitter accumulation in the proposed network with nine hierarchies is suppressed by about 1 dB more than in the conventional one, and this improvement becomes large in an MS network with a large number of levels. It is shown that the concept introduced can be applied to a general MS synchronization network which consists of a chain of PLLs (phase lock loops), e.g., to design the transfer function of the PLLs with a bandwidth reduced along the chain