Protocol control VLSI for broadband packet communications

Author

Ichikawa, Hiroyuki ; Yamada, Hiroki Y. ; Akaike, Takeshi ; Kanno, Shin ; Aoki, Makoto

Author_Institution

Commun. Switching Lab., NTT, Tokyo, Japan

fYear

1988

fDate

28 Nov-1 Dec 1988

Firstpage

1494

Abstract

Processing algorithms and architecture for a protocol control VLSI are presented. Parallel processing algorithms, buffer management functions, and direct execution of high-level protocol description language are introduced. The VLSI provides high-speed, high-throughput protocol processing for broadband packet communications systems. It uses CMOS technology and can handle X.25-based packet protocols (layers 2 and 3) at data rates of up to 50 Mb/s. The performance of a high-speed packet switching system incorporating this VLSI is evaluated

Keywords

CMOS integrated circuits; VLSI; broadband networks; packet switching; parallel algorithms; parallel architectures; protocols; 50 Mbit/s; CMOS technology; broadband packet communications; buffer management; data rates; high-level protocol description language; high-speed packet switching system; layer 2; layer 3; parallel processing algorithms; processing architecture; protocol control VLSI; Broadband communication; CMOS technology; Communication system control; Logic testing; Packet switching; Parallel processing; Protocols; Test pattern generators; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1988, and Exhibition. 'Communications for the Information Age.' Conference Record, GLOBECOM '88., IEEE

Conference_Location

Hollywood, FL

Type

conf

DOI

10.1109/GLOCOM.1988.26073

Filename

26073