An High Density Data Flash Based on Trapped Charge Programming and Erasing

With the exponential growth of digital consumer markets of digital cameras, feature phones, PDAs, personal computers, and portable digital audio/video players, there is high demand for ultrahigh density data storage flash. As the flash density increases to giga-bits (Gb), the critical dimensions are scaling down to sub-90nm. It is commonly understood that for 45 nm and beyond, the traditional floating gate (FG) flash will have retention issue due to tunnel oxide thinning. Trapped charge based non-volatile memory is one of the top choices to resolve the above scaling issue. Unlike FG flash that stores charge in conducting poly, the charge trapping flash stores charge in an insulating media (nitride in the case of SONOS and NROM). By localizing charges in two edges of cell gates over junctions, this kind of flash can hold twice as much data as standard flash without compromising device performance, endurance, and reliability. The cell operation uses channel-hot-electron (CHE) program, band-to-band hot hole (BTBHH) erase, and reverse read. In this paper, the authors present SMIC´s 90 nm double density flash (DDF) based on charge trapping in nitride. The figure shows the top view of a 2 Gb NAND flash manufactured in SMIC with cell efficiency up to 76%. The die size is 96 mm , which is one of smallest 2 Gb NAND to date. DDF process effectively integrates a 90 nm logic technology with cell width down to 105nm and 90 nm for 2Gb and 8Gb respectively. The cell is dual poly planarization (DPP) flat cell uses buried bit-line (BL) and contact-less virtual ground (VG). The flash memory adopts Co-salicide for low resistance word-line (WL) that eliminates the need for metal strapping that saves cost and enhances yield. Unlike traditional FG flash, this technology is free of erratic bits and it demonstrates good cell reliability