DocumentCode
3466314
Title
On the Connection of SRAM Cell Stability with Switching History in Partially Depleted SOI Technology
Author
Ji, Brian L. ; Hanafi, Hussein I. ; Ketchen, Mark B.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
788
Lastpage
791
Abstract
Read and write operational margins for SRAM cells in partially depleted silicon on insulator (PD-SOI) technology are studied. In both simulation and concept, cell stability is shown to be directly connected to the inverter nFET first switch/second switch history, thus linking SRAM margins to a PD SOI parameter that can be measured and monitored
Keywords
SRAM chips; logic gates; silicon-on-insulator; SRAM cell stability; inverter nFET switches; partially depleted silicon-on-insulator; Circuit stability; Delay; History; Inverters; Joining processes; Random access memory; Silicon on insulator technology; Switches; Switching circuits; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306508
Filename
4098235
Link To Document