Title :
Instabilities in deep submicron SRAM
Author_Institution :
Non-Volatile Static Memories Group, STMicroelectronics Pvt. Ltd., Noida
Abstract :
Scaling to nano scale CMOS has provided high density SRAM. Reduced cell area and increased density has created problem of standby leakage. Scaled down SRAM cell has more leakage and at high temperature it creates serious power issues. Application of leakage reduction methods generally lowers rail-to-rail voltage and hence reducing the stability of the cell. Reduction in cell node capacitance further increases the problem of soft errors
Keywords :
CMOS integrated circuits; SRAM chips; leakage currents; nanoelectronics; SRAM cell; cell node capacitance; leakage reduction; nanoscale CMOS; soft errors; standby leakage; CMOS technology; Capacitance; Design methodology; Guidelines; MOSFETs; Nonvolatile memory; Random access memory; Stability; Temperature; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306509
