A low power VLSI implementation for JPEG2000 codec

Author

Meng, Yicong ; Liu, Leibo ; Zhang, Li ; Wang, Zhihua

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

Volume

1

fYear

2005

fDate

24-27 Oct. 2005

Firstpage

198

Lastpage

202

Abstract

This paper proposed a low power VLSI implementation of JPEG2000 codec. Three power optimization schemes including gated clock, bus-invert and dual voltage scaling are adopted. An automated design flow for dual voltage scaling is also proposed. The JPEG2000 codec was fabricated in SMIC 0.18μm 1P6M standard CMOS technology. And it is capable of JPEG2000 compression/decompression with a 1280×1024 pixel (YUV422 full color) at 20frames/s employing a 100MHz operating frequency. The power consumption is reduced by 54% and is 465mW @ 1.8V and 100 MHz.

Keywords

CMOS integrated circuits; VLSI; codecs; digital signal processing chips; image coding; integrated circuit design; low-power electronics; 0.18 micron; 1.8 V; 100 MHz; 465 mW; CMOS technology; JPEG2000 codec; JPEG2000 compression; JPEG2000 decompression; automated design; bus-invert scaling; dual voltage scaling; gated clock scaling; low power VLSI implementation; power optimization schemes; CMOS technology; Circuits; Clocks; Codecs; Frequency; Image coding; Power dissipation; Transform coding; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611249

Filename

1611249