A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

Author

Rylyakov, A.V. ; Tierno, J.A. ; Turker, D.Z. ; Plouchart, J.-O. ; Ainspan, H.A. ; Friedman, D.

Author_Institution

IBM T.J. Watson, Yorktown Heights, NY

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

516

Lastpage

632

Abstract

We report two DPLLs fabricated in a standard 65 nm bulk CMOS process. One PLL, targeting 1-to-2 GHz clock generation for the ASIC consumer market, is realized using a 5-stage static CMOS-ring digitally-controlled oscillator (ring-DCO). The second PLL, an exploratory design for 20-to-30 GHz applications, is realized using an LC-tank DCO. Both PLLs use the same proportional-integral (PI) loop filter, DeltaSigma modulator (DeltaSigmaM), multi-modulus feedback divider and bang-bang phase and frequency detector (BB-PFD).

Keywords

CMOS digital integrated circuits; MMIC oscillators; UHF integrated circuits; digital phase locked loops; field effect MIMIC; field effect MMIC; integrated circuit design; 5-stage static CMOS-ring digitally-controlled oscillator; ASIC consumer market; DeltaSigma modulator; LC-tank DCO; bang-bang phase detector; bulk CMOS process; clock generation; frequency 1 GHz to 2 GHz; frequency 24 GHz to 32 GHz; frequency detector; modular all-digital PLL architecture; multimodulus feedback divider; proportional-integral loop filter; size 65 nm; Application specific integrated circuits; CMOS process; Clocks; Delta modulation; Feedback loop; Filters; Frequency conversion; Phase locked loops; Phase modulation; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523284

Filename

4523284