Title :
Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC
Author :
Kthiri, M. ; Loukil, H. ; Werda, I. ; Ben Atitallah, A. ; Samet, A. ; Masmoudi, N.
Author_Institution :
Nat. Sch. of Eng., Univ. of Sfax, Sfax
Abstract :
Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA.
Keywords :
field programmable gate arrays; motion estimation; video coding; AVC; FPGA; H.264; VHDL; fast block matching algorithm; hardware implementation; large diamond parallel search algorithm; motion estimation; video coding system; Automatic voltage control; Delay; Encoding; Field programmable gate arrays; Hardware; Motion estimation; Pipeline processing; Testing; Throughput; Video coding; FPGA; H.264; Hardware Implementation; VHDL; motion estimation;
Conference_Titel :
Systems, Signals and Devices, 2009. SSD '09. 6th International Multi-Conference on
Conference_Location :
Djerba
Print_ISBN :
978-1-4244-4345-1
Electronic_ISBN :
978-1-4244-4346-8
DOI :
10.1109/SSD.2009.4956714
