DocumentCode
3466418
Title
Drain Disturb Related to Negative VB in NOR flash
Author
Kai, Shi ; Mingzhen, Xu ; Changhua, Tan
Author_Institution
Dept. of Microelectron., Peking Univ., Shenzhen
fYear
2006
fDate
Oct. 2006
Firstpage
809
Lastpage
811
Abstract
In this paper, the effects of negative substrate bias on the drain disturb of NOR ETOXtrade flash EEPROM have been investigated. According to the quantity of the charge stored in the floating gate, the tests can be separated into two cases (CL: charge loss & CG: charge gain), and in some of the cases, an optimal negative substrate bias condition will be obtained as a trade-off between efficiency and reliability
Keywords
NOR circuits; flash memories; EEPROM; NOR flash memories; charge gain; charge loss; drain disturb; floating gate; negative substrate bias; Channel hot electron injection; Character generation; EPROM; Memory; Microelectronics; Stress; Testing; Thickness control; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306514
Filename
4098241
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