Author :
Wambacq, Piet ; Mercha, A. ; Scheir, K. ; Verbruggen, B. ; Borremans, J. ; De Heyn, V. ; Thijs, S. ; Linten, D. ; Van der Plas, G. ; Parvais, B. ; Dehan, M. ; Decoutere, S. ; Soens, C. ; Collaert, N. ; Jurczak, M.
Abstract :
CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.
Keywords :
CMOS integrated circuits; MOSFET; analogue integrated circuits; silicon-on-insulator; CMOS scaling; CMOS technology; FinFET; SOI; analog-circuit benchmarking; gate dielectric; planar bulk transistor; silicon-on-insulator; size 45 nm; CMOS analog integrated circuits; CMOS technology; Energy consumption; FinFETs; Frequency measurement; Gain measurement; Noise measurement; Power measurement; Radio frequency; Tuning;
