Title :
Low power SRAM design using charge sharing technique
Author :
Ming, Gu ; Jun, Yang ; Jun, Xue
Author_Institution :
Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., Nanjing
Abstract :
This paper describes a low-power write scheme by adopting charge sharing technique. By reducing the bit lines voltage swing, the bit lines dynamic power is reduced. The memory cell´s static noise margin (SNM) is discussed to prove it is a feasible scheme. Simulation results show compare to conventional SRAM, in write cycle this SRAM saves more than 20% dynamic power
Keywords :
SRAM chips; integrated circuit design; integrated circuit noise; low-power electronics; bit line dynamic power; bit line reduction; charge sharing technique; circuit simulation; low power SRAM design; low-power write scheme; static noise margin; voltage swing; Application specific integrated circuits; Capacitance; Energy consumption; Low voltage; MOSFETs; Power dissipation; Power engineering and energy; Random access memory; System-on-a-chip; Systems engineering and theory;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611260
