Title :
A G3 PowerPC/sup TM/ superscalar low-power microprocessor
Author :
Kennedy, A.R. ; Alexander, M. ; Fiene, E. ; Lyon, J. ; Kuttanna, B. ; Patel, R. ; Pham, M. ; Putrino, M. ; Croxton, C. ; Litch, S. ; Burgess, B.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
This microprocessor is a third-generation PowerPC microprocessor and is a member of the the G3 family of PowerPC processor products. Although its high performance (estimated at 10.0 SPECint95) makes it suited for high-end desktop systems, its low typical power dissipation of 5W and size of 66.5 mm/sup 2/ make it very attractive for portable systems as well. This microprocessor is a dual-issue superscalar machine with a four-stage pipeline, separate instruction- and data-side L1 caches (32 kBytes each), and full tags and support for up to 1 MByte of back-side L2. A thermal assist unit and I-cache throttling feature are included in the microprocessor as additional tools for thermal management. This microprocessor was designed in a 0.25-/spl mu/m CMOS process (0.18-/spl mu/m Leff) to operate at a frequency of 250 MHz.
Keywords :
CMOS digital integrated circuits; cache storage; microprocessor chips; power consumption; 0.18 mum; 0.25 mum; 1 MB; 250 MHz; 32 KB; 4-stage pipeline; 5 W; CMOS process; G3 PowerPC superscalar low-power microprocessor; I-cache throttling feature; SPECint95; back-side L2 cache; data-side L1 cache; dual-issue superscalar machine; high-end desktop systems; instruction-side L1 cache; operating frequency; performance; portable systems; power dissipation; size; tags; thermal assist unit; thermal management; Clocks; Decoding; Frequency synchronization; Ground penetrating radar; Hardware; History; Microprocessors; Monitoring; Performance analysis; Processor scheduling;
Conference_Titel :
Compcon '97. Proceedings, IEEE
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7804-6
DOI :
10.1109/CMPCON.1997.584742
