Hardware-software partition of fixed-point hardware accelerator from statistical perspective

With the advent of SoC (system-on-chip), a large of architecture have evolved for the viable implementation of hardware accelerators as a means of improving the performance of the complex algorithms used in the design of SoC circuits. And the concurrent design of hardware and software for SoC has displaced the traditional sequential design (Hakkennes and Vassiliadis, 2001). The SoC system architects define a system architecture consisting of cooperating system functions that form the basis of concurrent hardware and software design. This paper proposes a novel hardware-software co-design method for fixed-point hardware accelerator in SoC from statistical perspective. In any case, the proposed method has a very good result for real-time low cost devices, which is the biggest request in the market today