DocumentCode :
3466742
Title :
A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS
Author :
Shimizu, Yasuhide ; Murayama, Shigemitsu ; Kudoh, Kohhei ; Yatsuda, Hiroaki
Author_Institution :
Sony LSI Design, Nagasaki
fYear :
2008
fDate :
3-7 Feb. 2008
Firstpage :
552
Lastpage :
635
Abstract :
The ADC is fabricated in 90 nm digital CMOS process. The chip consumes 34 mW at 300MS/s (fin=fs/2) from 1.2 V analog/digital and 2.5 V T/H-switches supply. At 100 MS/s (fin= fs/2), it consumes 6.7 mW from 0.75 V analog/digital and 1.5 V T/H-switches supplies. FOMs are 780 fJ/conversion-step at 300 MS/s (fin=fs/2), 680fJ/conversion-step at 300MS/s (fin=2MHz), 350 fJ/conversion- step at 100 MS/s (fin=fs/2) and 290 fJ/conversion-step at 100 MS/s (fin=2MHz).The active area is 0.29 mm2.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; ADC; CMOS; power 34 mW; power 6.7 mW; size 90 nm; split-load interpolation-amplifier-array; voltage 0.75 V; voltage 1.2 V; voltage 1.5 V; voltage 2.5 V; word length 8 bit; CMOS process; Capacitance; Capacitors; Clocks; Energy consumption; Interpolation; Quantization; Sampling methods; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
Type :
conf
DOI :
10.1109/ISSCC.2008.4523302
Filename :
4523302
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3466742
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